A test pattern generator forms a part of an IC tester for testing semiconductor ICs and generates a test pattern to be applied to the IC under test and an expected value pattern for comparison with a response from the IC under test. These two patterns are commonly referred to simply as a test pattern.
A conventional test pattern generator is shown in FIG. 1. A clock PCK for pattern generating use and a start signal S are applied to an address generating circuit 11 and an address provided therefrom is used to read out a test pattern memory 12 in which a test pattern has been stored. The test pattern memory 12 is usually constituted by an SRAM (i.e. a static RAM).
A large-capacity test pattern memory is needed to cope with extended test patterns which result from an increased degree of integration of circuits to be tested and an automatic generation of test patterns by a computer. Conventionally, such a large-capacity test pattern memory employs the SRAM, and hence is expensive.
The number of transistors necessary for forming one memory cell is four to six in the case of the SRAM but only one in the case of a DRAM (i.e. a dynamic RAM). In the case of fabricating IC memories of the same chip area through a patterning process under the same rule, the IC memory using the DRAM is larger in capacity and lower in the unit cost per bit than the IC memory using the SRAM. Hence, the use of the DRAM will cut the manufacturing cost of the test pattern memory. However, stored contents of the DRAM will disappear unless refreshed at regular time intervals, and during the refresh the readout of a test pattern is suspended, making high-speed pattern generation impossible. On this account, the prior art does not employ the DRAM for the test pattern memory.
The present invention is to provide a test pattern generator which can be fabricated at low cost through use of the DRAM and is capable of generating test patterns at high speed.